Research Projects

• PDK Developement for IHP SiGe BiCMOS technology:  In this project, I am developing P-Cell libraries, schematics, and SPICE models for IHP-Opensource-PDK, and IHP commercial PDK

• Verilog-A code for 2D material based FETs: In this project, I have developed a Verilog-A code for 2D FET based circuit simulations. The  core model is a charge based explicit model that consideres the 2D DoS and Fermi Dirac distribution in account. The C-V model is derived using Ward-Dutton charge partitioning scheme.  The model is able to predict the electrical behaviour of the experimental TMD FET devices.

• Multiscal Simulation of 2D materials: In this project I have investigated the carrier transport in the 2D ink based printed network devices using the open source tool NanoTCAD ViDES along with Quantum Espresso and Wannier90.

• Analog Computation Circuits: I investigate novel analog circuits for neuromorphic computation and neural network implementation.

• 2D Nanosheet Transistor:  In this project, I have investigated the carrier transport in vertical stacked 2D-nanosheet transistors while considering the non-ideal effects like line-edge-roughness and contact resistances

List of Publications

Journal Papers: 

• P. K. Dubey , D. Marian , A. T.-Lopez , T. Knobloch , T. Grasser , G. Fiori, “Simulation of vertically stacked 2D nanosheet FETs,” IEEE Tran. Electron Devices, 2025, DOI: 10.1109/TED.2025.3533474.

• P. K. Dubey, S. Strangio, E. G. Marin, G. Fiori, G. Iannaccone, “A 2D-material FET Verilog-A model for analog neuromorphic circuit design” IEEE Transactions on Electron Devices, 2023, DOI: 10.1109/TED.2023.3298876.

• P. K. Dubey, D. Marian, G. Fiori, “Multi-scale simulation of 2D material ink based printed network devices.” IEEE Transactions on Electron Devices, vol. 70, no. 20, pp. 689-694, 2023. doi: 10.1109/TED.2022.3232082.

• P. K. Dubey, N. Yogeswaran, F. Liu, A. Vilouras, B. K. Kaushik, and R. Dahiya “Monolayer MoSe2 based Tunneling Field Effect Transistor for Ultra-Sensitive Strain Sensor” IEEE Transactions on Electron Devices, vol. 67, no. 5, pp. 2140-2146, 2020, DOI: 10.1109/TED.2020.2982732.

• P. K. Dubey, and B. K. Kaushik, “Evaluation of Circuit Performance of T-Shaped Tunnel FET,” IET Circuits, Devices & Systems, vol. 14. no. 5, pp. 667-673, 2020, DOI:10.1049/iet-cds.2019.0456.

• S. Joshi, P. K. Dubey, and B. K. Kaushik "Photosensor Based on Split Gate TMD TFET Using Photogating Effect for Visible Light Detection", IEEE Sensors Journal, vol. 20, no. 12, pp. 6346-6353, 2020, DOI: 10.1109/JSEN.2020.2966728.

• S. Joshi, P. K. Dubey and B.K. Kaushik, “A Transition Metal Dichalcogenide Tunnel FET-Based Waveguide-Integrated Photodetector Using Ge for Near-Infrared Detection”, IEEE Sensors Journal, vol. 19, no. 20, pp. 9187-9193, 2019. Available: 10.1109/jsen.2019.2922250.

• P. K. Dubey, B. K. Kaushik and E. Simoen, “Analytical modelling and device design optimization of epitaxial layer-based III–V tunnel FET”, IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 763-770, 2019. Available: 10.1049/iet-cds.2018.5169.

• P. K. Dubey and B.K. Kaushik, “A Charge Plasma-Based Monolayer Transition Metal Dichalcogenide Tunnel FET”, IEEE Transactions on Electron Devices, vol. 66, no. 6, pp. 2837-2843, 2019. Available: 10.1109/ted.2019.2909182.

• P. K. Dubey and B. K. Kaushik, “T-Shaped III-V heterojunction tunneling field-effect transistor,” IEEE Trans. Electron Devices, vol. 64, no. 8, Aug. 2017, DOI: 10.1109/TED.2017.2715853.